In general, a dynamic random access memory or DRAM is a semiconductor memory device using one capacitor and one transistor as data storage unit or unit cell. A logic one bit or “data” is saved in a DRAM as a charge in the capacitor. The transistor serves as a switch when reading and writing the “data” charged into the capacitor.
A general cell 1 of a DRAM is configured as shown in FIG. 1. In order to charge or save a logic one or “high” data value into a capacitor 2 of the unit cell 1, a high voltage is applied through a word line WL such that the transistor 3 can be turned on. When the transistor 3 is turned on, a “high” voltage or “data” is applied to node A (storage node) through a bit line BL. Thereafter, if the “high” data is charged into the capacitor 2, the voltage applied through the word line WL is changed into “low,” and the transistor 3 is turned off.
In the capacitor 2, however, the data charge is maintained over a limited time period due to leakage current. That is, charges stored in the capacitor 2 leak, causing the voltage VSN at node A to gradually decrease over time. Thus, in order to be able to read data from a DRAM, the voltage difference between both sides or plates of the capacitor, i.e., the voltage difference ΔV between a voltage VSN at node A and a cell plate voltage VCP, should be maintained as at least a minimum voltage ΔVMIN that is capable of being sensed by a sense amplifier.
Over time, the charge in the capacitor will leak until and the voltage difference ΔV between both ends of the capacitor becomes less (lower) than the minimum voltage ΔVMIN capable of being sensed by the sense amplifier after a certain period of time. In order to reduce such a phenomenon, the DRAM performs a refresh operation in which the charge on the capacitor 2 is actually restored or replenished, i.e., “refreshed.”
A In the self-refresh mode, a DRAM automatically performs a refresh operation for each predetermined cycle such that data in each cell can be maintained in a capacitor 2 of a cell.
For example, assuming that the self-refresh cycle time of a DRAM is 64 •, a refresh operation is performed for each corresponding cycle. Accordingly, the voltage difference ΔV between both sides of a capacitor of a cell is refreshed at a level of the minimum voltage ΔVMIN or more, which can be sensed by a sense amplifier, for each at least 64 •.
A self-refresh cycle is determined to be a predetermined cycle by expecting the charging capacity of a cell in advance. However, if a refresh cycle is too long or too short as compared with the substantial charging capacity of a cell, there might be a problem in that the capacity of the cell is not appropriately used, or a large amount of current is consumed.
Further, in a case where a refresh cycle is changed depending on a temperature, there is required a circuit generating pulses for controlling a change in refresh cycle by sensing a temperature, and a self-refresh circuit occupies an additional area as large as the circuit. Therefore, there is a problem in that efficiency is lowered in view of a cell layout.